1. Field of the Invention
The present invention generally relates to a wiring substrate having one of faces being roughened and an alignment mark, a manufacturing method of the wiring substrate, and a semiconductor package having the wiring substrate on which the semiconductor chip is mounted.
2. Description of the Related Art
An example of a build-up substrate is described. There is an example of a wiring substrate made by a build-up manufacturing method. FIG. 1 is a cross-sectional view of a part of the example wiring substrate manufactured by the build-up manufacturing method without having a core (coreless wiring substrate). The coreless wiring substrate 100 has a structure in which first wiring layers 110, a first insulating layer 120, second wiring layers 130, and a second insulating layer 140 are sequentially laminated.
In the wiring substrate 100, the first wiring layers 110 are provided inside recesses 120y formed on one side of the first insulating layer 120. Faces 110s of the first wiring layers 110 are exposed from the recesses 120y. The first wiring layer 110 includes the electrode pad 110a and an alignment mark 110b. The electrode pads 110a are used as connection terminals connected to a semiconductor chip. The alignment mark 110b is used as a standard for aligning electronic components such as the semiconductor chip with the wiring substrate 100, a standard for aligning the wiring substrate 100 with another wiring substrate, or the like.
Second wiring layers 130 are formed on the opposite side of the first insulating layer 120. The second wiring layers 130 are made of vias which penetrate through the first insulating layer 120, fill inside first via holes 120x, and expose upper surfaces of the vias; and an interconnection pattern formed on the face of the first insulating layer 120. The second wiring layers 130 are electrically connected to the electrode pads 110a exposed toward the first via holes 120x. 
The second insulating layer 140 is formed to cover the second wiring layers 130 on the first insulating layer 120. It is possible to further laminate other wiring and insulating layers when necessary.
Next, a manufacturing method of the wiring substrate 100 is described. FIG. 2 thru FIG. 5 illustrate manufacturing processes of the example semiconductor device illustrated in FIG. 1. In FIG. 2 to FIG. 5, the same reference symbols are attached to the same parts and descriptions of these parts are omitted. Referring to FIG. 2, a supporting body 210 made of a copper foil is prepared. On one surface of the supporting body 210, a resist layer 220 is formed having opening portions 220x corresponding to positions in which the first wiring layers 110 are formed.
Referring to FIG. 3, metallic layers 230 and the first wiring layers 110 are laminated on one of the surfaces of the supporting body 210 by an electrolytic plating method using the supporting body 210 as a power supplying layer. The material of the metallic layers 230 may be nickel (Ni). The material of the first wiring layers 110 may be copper (Cu) or the like. The faces 110s of the first wiring layers 110 are in contact with the faces 230s of the metallic layers 230.
Referring to FIG. 4, after removing the resist layer 220 illustrated in FIG. 3, the first insulating layer 120 is formed so as to cover the metallic layers 230, the first wiring layers 110, and the surface of the supporting body 210. After forming the first via holes 120x on the first insulating layer 120, the second wiring layers 130 electrically connected to the first wiring layers 110 are formed on the first insulating layer 120 through the first via holes 120x. The second insulating layer 140 is formed to cover the second wiring layers 130 on the first insulating layer 120, and other wiring and insulating layers when necessary.
The supporting body 210 illustrated in FIG. 4 is removed in the process illustrated in FIG. 5. An etching liquid capable of removing the supporting body 210 made of the copper foil and not capable of removing the metallic layers 230 is used. With this, the metallic layers 230 function as etching stopper layers to enable removing only the supporting body 210.
Next, the metallic layers 230 are removed by etching using an etching liquid which can remove only the metallic layers 230 made of nickel (Ni). With this the faces 110s of the first wiring layers 110 are exposed to the outside and the wiring substrate 100 illustrated in FIG. 1 is completed.
The faces 230s of the metallic layers 230 made of nickel (Ni) and formed by an electrolytic plating method are ordinarily flat. Therefore, the faces 110s of the first wiring layers 110 including the electrode pads 110a and the alignment mark 110b in contact with the faces 230s of the metallic layers 230 which are exposed after the process illustrated in FIG. 5 are also flat. The surface roughness Ra of the flat faces is 50 nm or less (Ra≦50).
As described above, the alignment mark 110b is used as a standard for aligning electronic components such as the semiconductor chip with the wiring substrate 100, a standard for aligning the wiring substrate 100 with another wiring substrate, or the like. If the face 110s of the alignment mark 110b is not flat, there occurs a problem that the semiconductor chip and the wiring substrate 100 are not properly aligned. Referring to FIG. 6, the problem is described.
FIG. 6 illustrates reflection of light by the example alignment mark 110b. Referring to FIG. 6, the same reference symbols are attached to the same parts and descriptions of these parts are omitted. FIG. 6 illustrates the opposite cross-sectional view of the wiring substrate 100. The electrode pads 110a are used as connection terminals connected to a semiconductor chip. The semiconductor chip is installed on the side of the electrode pads 110a of the wiring substrate 100 while aligning the semiconductor chip with the wiring substrate 100.
Referring to FIG. 6, when the semiconductor chip (not illustrated) is aligned with the wiring substrate 100, a light source 910 irradiates a visible light or the like on faces 110s of the alignment mark 110b. The light reflected on the faces 110s is received by a light receiving unit 920 of a CCD camera or the like to thereby recognize the alignment mark 110b. Based on the recognized alignment mark 110b, the semiconductor chip (not illustrated) is aligned with the wiring substrate 100. Since it is necessary to arrange the light source 910 at a position in which the light source 910 does not obstruct the light receiving unit 920, the irradiating light may obliquely impinge on the face 110s of the alignment mark 110b. 
When the face 110s of the alignment mark 110b is flat, the irradiating light from the light source 910 scarcely causes diffused reflection on the face 110s. Therefore, most of the irradiating light from the light source 910 becomes reflection light having a reflection angle (angle between the reflection light and the Z axis) substantially the same as an incident angle (angle between the irradiating light and the Z axis). Thus, the reflection light is not directed toward the light receiving unit 920 and is directed in the arrow direction in FIG. 6. As a result, most of the irradiating light from the light source 910 does not impinge on the light receiving unit 920. Therefore, it is difficult to recognize the alignment mark 110b. When the alignment mark 110b is not recognized, there occurs a problem that the semiconductor chip cannot be installed on the wiring substrate 100.    [Patent Document 1] Japanese Laid-open Patent Publication No. H10-125819    [Patent Document 2] Japanese Laid-open Patent Publication No. 2002-198462    [Patent Document 3] Japanese Laid-open Patent Publication No. 2009-033183